The Xelic Optical Transport Network (OTN) ODU4 Flex Single Level Multiplexer Core (XCO4FMX) performs tributary timeslot interleaving and switching of independent ODU0, ODU1, ODU1e, ODU2, ODU2e, ODU3, and ODU Flex data streams and maps them into an ODU4 frame structure using generic mapping procedure (GMP) justification methods. Support is also provided to map/demap incoming ODU4 frames into an ODU4+ (overclocked) rate signal. OPU4 multiplex overhead is inserted and justification control is provided based on incoming request signaling. Incoming line side OPU4 overhead is interpreted with error and justification detection reported. Client and line side data is transferred using a data valid scheme and operates at rates up to 180MHz. The XCO4FMX Transmit Processor contains eighty client side FIFO’s with overflow/underflow detection.
Incoming ODU0, ODU1, ODU1e, ODU2, ODU2e, ODU3, and ODU Flex data streams are interleaved and switched to 1.25G timeslots using generic mapping procedure (GMP) justification methods. Justification control is provided through incoming request signaling. Payload Structure Identifier (PSI) field insertion is provided and contains payload type (PT 21 supported), multiplex structure identifier, and reserved bytes multi-frame information. Client data signal multiplexing of up to 80 ODU0’s, 40 ODU1’s, 10 ODU2’s, 2 ODU3’s, 3 ODU1e’s (4 ODU1e’s if overclocking), 3 ODU2e’s (4 ODU2e’s if overclocking) and 80/ts ODU Flex signals is supported. FAS and MFAS information is inserted into outgoing frames in addition to all OPU4 overhead fields. FAS and MFAS indicator signaling is also provided at the line side interface.
The XCO4FMX Receive Processor contains a frame position counter synchronized to incoming FAS and MFAS frame indicator signaling. OPU4 overhead is extracted from incoming frames and interpreted with various error conditions reported to an internal maskable interrupt register. Positive and negative justifications are detected and reported though output signaling and internal interrupts. Tributary timeslot de-interleaving is performed on incoming ODU4 frames. Incoming GMP Cm and CnD information for each tributary port is provided at the client side interface for client clocking considerations.
Performance counters (configurable for interval count capture or latch and clear operation) are provided for the accumulation of inserted (XCO4FMX transmit processor) and detected (XCO4FMX receive processor) positive and negative justification events. Counters are saturating with latch and clear operation or periodic error sync autoupdate mode.
The XCO4FMX provides Transmit Processor terminal loopback and Receive Processor facility loopback modes of operation for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO4FMX core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Provides transmit and receive loopback options for diagnostic purposes.
- Supports multiplexing of up to 80 ODU0’s, 40 ODU1’s, 8 ODU2’s, 40 ODU1e’s, 8 ODU2e’s, 2 ODU3’s,
- or 80/ts ODU Flex signals.
- Incoming ODUk data streams are distributed over 1 or more 1.25G timeslots using generic mapping
- procedure (GMP) justification methods.
- Flexible OPU overhead field insertion is provided with PT 21 support.
- Provides justification through incoming request signaling.
- Inserts FAS/MFAS/OMFI framing information with output signaling provided.
- Programmable positive and negative justification counters provided with user defined interval or errored
- second accumulation.
- Performs OPU4 tributary 1.25G timeslot de-mapping into ODUk frames.
- Supports GMP justification methods.
- Provides configurable FIFO’s for ODUk data streams.
- Contains frame position counter synchronized to incoming FAS/MFAS/OMFI signaling.
- Provides saturating counters for positive, double positive, negative, and double negative justifications
- detected with programmable latch and clear or incoming error sync capture configurations.
- Interprets and extracts incoming OPU4 overhead information and reports errors to internal register with
- maskable interrupt capability.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).