The Parallel Turbo decoder IP core meets the requirements as per the 3GPP standards. The conventional Turbo decoding algorithm is modified to meet the performance as per the 3GPP standards. Here modified MAX LOG MAP algorithm is implemented. High throughput requirements for LTE-A features like Carrier Aggregation (CA) and SU-MIMO have put a constraint on latency of turbo decoding in receiver chain. Main contributing factors include ‘Iteration count’ and ‘latency of single decoder’. Our efforts focus on reducing the latency of the decoder significantly without much change in iteration count and convergence. Windowing approach is followed. Our Turbo decoder IP will help customers implement their application faster with less time to market
- 3GPP TS 36.212 V 10.5.0 LTE/ LTE Advanced (LTE A) specification compliant.
- Full 3GPP block size range supported 40 – 6144.
- Input bit size 6bits or 8bits supported.
- Parallel architecture, 2 MAP decoders can be operated in parallel.
- Support for Rate 1/3 coded input.
- Two’s complement data/parity input.
- Configurable number of iterations.
- Supports fast termination option.
- Low gate count & memory usage.
- Supports Xilinx , Altera FPGAs
- Available in Verilog HDL, VHDL code can be delivered on request.
- Bit accurate C and MATLAB models are available.
- As the turbo decoder operation is iterative and time consuming we have made an innovation by splitting the SISO module into 2 parallel units. This reduces our total latency by half.
- Netlist, verilog or VHDL code.
- Target technology – Xilinx, Altera devices
- Test bench
- Matlab , C, Verilog simulation models available
- Detailed technical documentation.
- Applications with the need for a wide range of code rates and block lengths
- Applications with highest demands on forward error correction
- Satellite communication
Block Diagram of the Parallel Turbo decoder for LTE and LTE-A