The DesignWare® Dual Mode (DM) IP for PCI Express® implements the port logic required to build a Root Complex (RC) or Endpoint (EP) device. The configurable and scalable DesignWare DM is compliant to the PCI Express 3.0, 2.0 and 1.1 and PIPE specifications. The high quality, synthesizable IP is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimizing size, power, and throughput specific to match the needs of your application. The DesignWare DM integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies.
The silicon-proven DesignWare DM core has been extensively validated with multiple hardware platforms, PHYs and PCIe verification suites thereby reducing risk and improving time to market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications. The DesignWare IP for PCI Express is used to power the industry’s PCI Express compliance testing at PCI-SIG Compliance Workshops.
Available in 32, 64, 128 and 256 bit data path widths for maximum flexibility
Low latency and gate count
Optimal on-chip memory utilization
Bypass, cut-through and store-and-forward receive queues
Legacy PCI, MSI and MSI-X interrupt support
Designed according to the PCI Express 3.0, 2.0 and 1.1 specifications, including the latest errata and ECNs
Supports PIPE 3.0 interface definition
Supports 8.0, 5.0 and 2.5 Gbps line rates
Architecture supports x1, x2, x4, x8, and x16 lanes
coreConsultant utility to guide you through the installation, configuration, verification, and implementation of the core
ASIC and FPGA synthesis scripts
Core verification environment and DesignWare Verification IP for PCI Express
Documentation: Release notes, Installation/integration guide, Application notes, User Manual
Video Demo of the PCI Express 2.0 Dual Mode - 32 bit (x1,x4), 64-bit (x2,x4,x8)
Synopsys DesignWare IP for PCI Express 2.0 Complete Solution Demo
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