The PCI Express Endpoint Controller Core is compliant with PCI Express Base specification 1.0a, including the Transaction, Data Link, and Physical protocol layers.
The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications—x1 (single lane) and x4 (four lane)—and offers bi-directional data rates from 250MB/s (x1) to 1GB/s (x4). It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, and power management features. Multi-lane versions of the core support lane reversal and polarity inversion.
The core has an Application Interface (AIF) layer that makes integration significantly easier by relieving the designer from the complexity of transaction layer packet (TLP) handling. This AIF includes a DMA controller and handles the TLP encoding and decoding, and provides an interface to popular system buses, including Wishbone and AMBA™ AHB, AXI, and AXI4.
The external connection interface from the core conforms to the Intel® PIPE specifica-tion, ensuring compatibility with any 16-bit PIPE-compliant physical layer (PHY). The core has been successfully used with PHYs from multiple vendors.
The synchronous, latch-free core design was rigorously verified for compliance with the PCI Express specification, and has passed PCI-SIG certification. The core has been tested for interoperability with multiple motherboards using chipsets from various ven-dors, and is in use by multiple customers.
- * Compliant with PCI Express Base Specification 1.0a
- * Implements Transaction, Data Link, and Physical protocol layers in hardware
- * Supports x1 and x4 link widths
- * Offers a data rate of 2.5 Gbps per lane
- * Supports up to eight Virtual Channels
- * Supports lane reversal and polarity inversion
- * PCI Configuration space type 0 header
- * MSI capability support
- * End-to-end cyclic redundancy code (ECRC) generation and checking support
- * Advanced Error Reporting capability support
- * Configurable TLP data payload size, from 128B to 4BB
- * Configurable size for the Transmit Retry and Receive data buffers
- * Modular architecture
- * Synchronous design
- * 64-bit internal datapath at 125MHz
- * Application Interface (AIF) for easier system integration using industry standard bus interfaces (e.g., Wishbone, AMBA); handles up to 8 DMA channels
- * Conforms to standard PIPE interface for compatibility with any 16-bit PIPE-compliant PHY
- * This core has passed the PCI-SIG PCI Express compliance tests, and appears on their Integrators List.
- * ASIC cores: HDL RTL source of the CPXP-EP and CPXP-EP-AIF
- FPGA cores: Post-synthesis EDIF netlist of the CPXP-EP and CPXP-EP-AIF
- * Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- * Simulation script, vectors, expected results, and comparison utility
- * Synthesis or place and route script
- * Comprehensive user documentation