Synopsys' DesignWare® PCI Express 1.1 PHY is a complete mixed-signal semiconductor IP solution, designed for integration in root complex, endpoint, dual-mode, and switch applications. The PCIe PHY includes all of the required logical and physical design files needed for integration in a SoC design. Industry standard PIPE interface and validated compatibility with the DesignWare PCIe Endpoint Digital Controller enable easy integration of the PCIe solution into a variety of applications, in high end compute, server, data center, consumer and graphics markets. The PCIe PHY integrates high-speed mixed-signal custom CMOS circuitry compliant with the PCIe 1.1 base specification and the PIPE interface standard. While extremely low in power consumption and area requirements, the DesignWare PCI Express PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. Synopsys provides designers with a complete, silicon-proven PCI Express 1.1 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 2.5 Gbps PCI Express interface into their high performance SoC designs.
- Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies.
- Supports a wide range of PCI Express bus widths (up to x16 support).
- Fully compliant with PCI Express 1.0a and 1.0a Errata and PIPE interface to ensure interoperability and ease of integration with higher protocol levels.
- Supports all power-down states for highly efficient operation.
- Full support for beaconing, receiver detection and electrical idle.
- Reliable link operation across channel manufacturing operation (BER<10-18).
- Unique, built-in diagnostics enables visibility into link performance.
- Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing.
- Silicon proven for popular 130nm, 90nm and 65nm processes with roadmap to 40nm processes.
- GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report.
- Simulation model for digital blocks, Behavioral models for analog blocks.
- Synopsys' PrimeTime STA results, Gate-level netlist and SDF timing file.
- DesignWare PHY Hard Macro Databook for PCIe.
- BSDL files for JTAG AC/DC Boundary Scan, ATE test vectors.