The Flash DLL PHY supports 4 different DDR Flash Standards: ONFI 2, ONFI 3, Toggle 1, Toggle 2. In addition the PHY supports a bypass mode to support asynchronous Flash memories including ONFI 1. The DLL DDR PHY is an all-digital solution connecting the DDR I/O pads to the DFI interface of the memory controller including alignment of write data, read data capture, and DQS gating. By using an all-digital DLL-based design, both power and area are kept to a minimum, typically under 4mW per data slice for ONFI 3 mode 5 .
Features
- Read and write data interfaces employing DLL based delays for correct data and dqs alignment
- Digital DLL design creates PVT-compensated read and write clocks to the appropriate data paths
- Address and control interfaces for ONFI 2,3/ Toggle 1,2
- 8-bit datapath slice can be repeated to build PHY's of any width
- Individual timing to each data slice supports ONFI 2,3/ Toggle 1,2
- Register interface for PHY programming, configuration, and testing modes
- Clock gating for low power operation
- Scan functionality for data slice
- Internal and external data-path loop-back mode for additional functional testing
- Boundary scan muxing built into core logic to facilitate insertion of boundary scan chains between core logic and IO pads
- Natively low-latency design
Benefits
- The memory subsystem is a core component to any SoC, and the DDR Flash ONFi 1,2,3 and Toggle 1,2 interface will fundamentally impact the performance and cost of your system. Cadence's DDR Flash solution is the only fully integrated IP offerings in the market with the features and configurability required to optimize your design and meet your performance, power, and cost targets. With design wins ranging from the lowest-power handheld consumer applications to the highest-performance enterprise supercomputers, Cadence's DDR Design IP is your lowest risk path to success.
Deliverables
- Simulation and Implementation
- Synthesizable RTL Verilog files for all PHY modules including data slice.
- Verilog modules of IO pads
- Sample IO pad instantiation of PHY signal pads complete with all core logic connections to the IO pads.
- Verilog sample test bench with Denali memory models, encrypted memory controller, and sample tests. This includes an automated script to compile and run this test bench.
- Register configuration files and utilities for programming the sample simulation test bench, controller, and PHY registers.
- Documentation
- PHY users guide
- PHY level implementation guide
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