The Internal Synchronous SRAM Controller provides a method of communicating with an integrated Synchronous Static Random Access Memory (SSRAM). The SSRAM array comes in byte, half-word (double byte), and word (four bytes) widths and various depths. The default configuration is two kilowords where each word is 32 bits wide (2K x 32). The memory interface allows word, half-word, or byte wide addressing.
The Internal Synchronous SRAM Controller is compatible with AMBA® 2.0 AHB bus systems.
- Byte, 16 bit half-word, or 32 bit word access
- AMBA® 2.0 AHB compatible
- Fully scalable
- Optional Byte steering logic
- PiP-AMBA Library Core
Block Diagram of the Internal Synchronous SRAM Controller