The Performance ESP/AH (IPsec) Processor features a new enhanced architecture that can be scaled to achieve up to tens of Gbps of ESP/AH packet processing required for the IPsec Layer 3 security protocol.
The level of protocol processing and the addition of Security Association (SA) management by the protocol engine directly in system memory minimize the overhead on the host processor, thus allowing today’s high bandwidth requirements to be easily achieved in a wide range of networking applications. The highly configurable LLP-130 offers many attractive features and is targeted at a variety of networking applications including residential, enterprise and SMB gateways, VPN appliances, data centers, PONs and network edge routers.
Please note that the LLP-130 requires memory instances for data and contexts which is not include in the gate count. Please contact Elliptic for more information on the memory requirements.
- Highly configurable, silicon-proven
- Complete ESP and AH packet transforms, including header insertion and removal
- Supports IPv4 and IPv6 protocols; Supports tunnel and transport modes
- Adds or strips padding
- Replay check with 32, 64, 128 or 256 packet window
- Built-in scatter/gather DMA capability offloads system CPU; Optimal bus utilization
- Increased throughput with parallel hashing and encryption
- Command and status FIFO depth selection allows interrupt coalescence
- Dual-clock domain capability to run cryptography content in a different clock domain; Support for big- or little-endian
- Configurable 32- or 64-bit bus interfaces: ARM® AMBA® AXI4™ (low power) and AHB; Lower level of interfacing
- Verilog HDL
- Testbench and sample simulation script
- Sample synthesis script and constraints
- Sample Linux™ drivers and test tools