The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation can be pipelined up to 9 levels. Input data are fed every clock cycle. The first result appears after 9 clock periods latency and next results are available each clock cycle. Precision and accuracy are parameterized.
DFPSQRT is a technology independent design that can be implemented in a variety of process technologies.
- Full IEEE-754 compliance
- Single precision real format support
- Simple interface
- No programming required
- 9 levels pipeline
- Overflow, underflow and invalid operation flags
- 24-bit accuracy, 6 fractional decimal digits
- Results available at every clock
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready