ChipWare: Provides either signed (two's complement) or unsigned multiplication based on the TC input control signal. It also provides for automatic pipelining. The number of pipeline stages is controlled by the stages parameter. The function of the design is therefore, Z(i)=A(i-stages)×B(i-stages). This equation represents both the computation of the circuit and the latency of the circuit. When the TC input is 0, unsigned multiplication is performed. When the TC input is 1, signed multiplication is performed. The width of the A and B inputs is controlled by wA and wB respectively. The width of the Z output is determined by wA+wB. The TC control input is a one-bit input signal. Z(i) is the value signal Z at the i'th clock cycle. The CW_mult_n_stage design can be thought of as an CW_mult followed by an CW_pipe_reg. In fact, this is exactly how the simulation model is constructed. The actual circuit structure pushes the pipeline registers into the multiplier to provide significantly reduced critical path delay.
- This IP is available as part of Cadence Encounter RTL Compiler XL