The PLB Arbiter consists of a central bus arbiter, the necessary bus control and gating logic, and all necessary bus OR/MUX structures. The PLB Arbiter provides the entire PLB bus structure and allows for direct connection for up to 16 masters and 16 slaves and supports 64 or 32 bits for master and slave devices. The PLB Arbiter consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a three-cycle-only arbitration feature. It also contains a DCR slave interface to provide access to its bus error status registers. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
- Ideal for designing high performance embedded systems using PowerPC™ core in Virtex-II Pro™
- Provides complete PLB bus structure
- Arbitration support for up to 16 masters
- Design Tools Support: EDK