The PL0064 is a mixed-mode custom LC-VCO phase locked loop (PLL) block targeted for the TSMC 65nm LP process.
The digital portion of the design is used for PLL calibration, dividing the reference clock, detecting lock and generating the lock indicator, and analog test point decoding.
The analog portion of the design is an LC-VCO PLL coupled with a differential-to-single ended clock buffer and ADC and DAC clock dividing capability. This block contains 1.2V-to-2.5V level translators, phase frequency detector (PFD), charge pump (CP), loop filter, voltage controlled oscillator (VCO) bias generator, VCO, divide-by-two VCO clock divider, feedback clock divider, and differential analog test point generation.
The PLL is intended for integer-mode only operation. Performance specifications herein apply only to integer-mode operation. Fractional capability is built into the PLL for test purposes only.
- 25MHz through 650MHz reference clock support
- Differential, single-ended, and AC-coupled reference input clock
- Programmable reference pre-divider
- Bypass mode
- 6 programmable output clocks
- Output enables for differential and high drive output clocks
- Bypass mode supported for all clocks
- Reference clock output
- Programmable charge pump gain
- Programmable loop-filter bandwidth
- VCO range: 3.75GHz – 4.6GHz
- Low jitter output clocks
- Fractional or integer feedback divider
- Locked indicator
- Low-power shutdown mode
- Analog test bus for internal test point static analysis
- Industrial operating temperature range: -40C to +125C
- Standard Integration Views
- Intergration Support