Progressive Re-Processing IP Core

The Progressive Re-Processing IP Core is designed specifically to improve progressive video signals by removing the artifacts caused by inferior interlaced-to-progressive conversion. Video signals that originate in the interlaced format used by most broadcasters often suffer degradation when the signal is converted to the progressive format required by digital displays. If this process is not done well, it results in artifacts which will be amplified during scaling or other processing such as detail enhancement. The Progressive Re-Processing IP Core addresses this problem be reverting the progressive video signal to its original interlaced format so that it can be reconverted to progressive using a higher-quality deinterlacer.

The Progressive Re-Processing IP Core is targeted for use in SoCs for DTVs, computer displays or A/V receivers (sink devices). These devices receive video signals from sources located in front of the video processing chain, such as a set-top box. If the video signal delivered by these sources is poorly deinterlaced, the subsequent device which includes the PReP IP core is able to reprocess the incoming video signal resulting in improved quality. For this functionality, the IP core is placed before the deinterlacer in the video SoC.

The Progressive Re-Processing IP Core works with 8-, 10-, or 12-bit color depth and processes 480p, 576p, 1080p50, and 1080p60 sources. The PReP process can be easily controlled via software.