Quad Full HD / 3D Full HD Display Processor IP Core
The Quad Full HD / 3D Full HD Display Processor IP Core is the final module of a digital video path intended for use in real-time multi-display systems. The controller has been optimized for high-end mobile devices through implementation of advanced power reduction methods.
The design provides a very wide range of video formats, starting from small resolutions like QVGA, PAL/NSTC and ending with Quad Full HD or DCI 4K formats. The maximum video resolution supported in the design is limited by the manufacturing technology.
The design supports different color spaces of the image and video signals like YUV with several subsampling modes (4:2:2 and 4:2:0) and RGB (4:4:4) with alpha-blending capability.
The Quad Full HD / 3D Full HD Display Processor is equipped with the AMBA® AXI master interface to provide efficient communication with the system memory. Flexible and easy programming of the display processor is provided through two AMBA® APB interfaces – one for general purpose and the other for secure access.
Programmable custom display resolution up to
Support for selected 3D HDMI formats
On-the-fly composition of up to 3 video or graphics layers
Interoperability with ARM TrustZone® environemt – protection of display layers parameters, secure APB interface
Plethora of supported RGB and YUV pixel formats: ABGR 2-10-10-10, ARGB 8-8-8-8, RGB 8-8-8, YUV 4:2:2, YUV 4:2:0 and others
Progressive or interlaced video input
Parallel RGB output interface featuring up to 12 bits per component with HSYNC, VSYNC and blanking signal
HDMI and MIPI DPI compatible interface
AMBA® AXI4 read master interface for communication with a system memory
Two AMBA® APB slave interfaces for configuration
One common interrupt output
AMBA® AXI4 Low-power interface
Programmable display formats according to VESA or CEA standards, or specific user requirements
Significant CPU off-load from video processing tasks
Variety of operation modes and even more programmable parameters
AXI4-enabled high-performance and low latency solution
Compatibility with all ARM video and graphics processors
Support for ARM TrustZone® environment
Verilog source code
Synthesis support (Synopsys®, Cadence®) with a complete set of synthesis scripts
Simulation support (Mentor Graphics®, Cadence®) with a full set of scripts and macros
Extensive test bench
Video Demo of the Quad Full HD / 3D Full HD Display Processor IP Core
PANTA DP20 Demonstation Board Overview
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