The Quad Serial Flash Controller provides an interface to Serial Flash and Serial Devices. The Quad Serial Flash Controller has an AHB Master/Slave interface to connect to SoC. The data from the serial devices (Flash or any serial Peripheral) can be transferred from using register I/O. The Quad Serial Flash Controller can work up to 100 MHz of serial interface. So to ensure less overhead for the Host processor controlling the transfers, multiple commands can be queued. The Quad Serial Flash Controller can queue up to 16 commands and will have 16 deep data buffer for data transfer. The Quad Serial Flash Controller is designed to meet timing very easily at all the interfaces.
- SPI Master Interface at 133 MHz
- Supports Single ,Dual SPI and QUAD SPI mode
- Programmable Command Sequence
- Master Clock derived from the AHB (System) Clock
- Supports all Command types (Read, Fast/Dual/Quad Read SDR/DDR, Page Program, Quad Page Program, Erase etc.)
- Supports mode0, mode3
- Programmable CPOL, CPHA
- Individually Controllable pins to drive chip-select, write protect and hold signals
- Supports Scatter Gather DMA and Programmed IO mode for Data Transfer
- Threshold to generate interrupts
- The IP can be configured to have 4 to 16 Command/Data buffers.
- System Interface up to 300 MHz
- Less gate counts 8K
- All flash modes are supported
- Easily integrated into SoC
- Customizable interfaces
- World class customer support
- Fully Synthesizable RTL code.
- Architecture Specification & Integration Manual.
- Self-checking Test bench and Testcases
- Simulation Scripts -NC - Verilog , Modelsim , VCS , Questa Sim,
- ASIC/FPGA Synthesis Scripts.
- User Documentation and Integration manual
Block Diagram of the Quad Serial Flash Controller