To maintain or increase their strength on the market, manufacturers of high density consumer and nomadic devices must regularly offer more features to their end customers - while maintaining competitive pricing. Finding the best compromise between low power and cost reduction is a significant challenge for SoC designers.
The single port memory array Haumea meets the most demanding power budgets thanks to its smart low power design and its power reduction features. Haumea also allows cost reduction thanks to its high density architecture and Design for Yield.
In the 130 nm technological node, Haumea is offered for SMIC, TSMC and T-Like foundries. A Dual Port variant of this architecture is available.
- Power reduction features
- Decrease of fabrication costs
- Optimal Design for Yield