The LP-Serial Endpoint Core implements all of the functions are defined in the RapidIO Physical Layer LP-Serial Specification Rev. 2.1. Figure 1 illustrates the overall architecture of the core.
The Buffer/Mux module supports up to three ports for logical layer functions available from Praesum or user defined.
This simplifies connectivity when multiple local interfaces must be supported. The demultiplexing of incoming traffic to the LocaLink Rx ports is user defined. In addition to the RapidIO Physical layer functions, the core also includes Management Module that supports access to Physical, Transport, and Logical Layer CSRs either through maintenance transactions, or through the Alternate Management Interface (AMI).
- Implements the complete RapidIO Physical Layer LP-Serial protocol.
- Compliant with Rev. 2.1 of the specification
- Implements RapidIO Error Management Extensions
- 64-bit internal data paths.
- Supports 1x, 2x, and 4x link widths.
- Hardware error recovery.
- Flexible SERDES interface supports industry standard multi-gigabit serial transceiver blocks.
- Integrated buffer module for transmit and receive packet buffering.
- Supports three user side LocaLinkTM transmit and receive interfaces for connection to logical layer functions.
- Management Entity with integrated decoder for RapidIO maintenance transactions.
- Management Entity supports optional soft packet interface which enables software implementations of logical layer functions.