The RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The The RapidIO Controller can be used as a Host or device. The RapidIO Controller when used along with the RapidIO to AXI Bridge (RAB) provides speed multi-channel DMA, Data Message and Data streaming functionality to match the bandwidth requirements of the RapidIO interface.
The RapidIO Controller is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RapidIO solution provides highly scalable bandwidth through a configurable data path width and clock frequency.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.
Features
- Compliant with RapidIO specification, Revision 2.2
- Supports both Serial and Parallel interfaces
- Supports 1x and 4x serial interfaces at 1.25/2.5/3.125/5/6.25Gbps
- Supports 8 and 16 bit parallel interfaces at 250/375/500 MHz
- Implements physical, transport and logical layer functions
- Supports both input/output and message passing protocols
- Implements receiver controlled flow control
- Supports all transaction flows and priorities
- Support for up to 256 bytes data payload
- Supports 34 & 50 bit addressing
- Implements a flexible buffer management scheme
- Performs link initialization, training, error detection and recovery
- Performs auto detection of interface widths and modes
- Targets FPGA, Structured ASIC and Standard Cell technologies
- Supports 64 bit Datapath
Benefits
- Superior architecture-optimized for high performance, link utilization, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with RTA VIP
Deliverables
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- Documentation
Block Diagram of the SRIO Native Controller with V2.2 Support
Talk to us
Add your Products