Despite dynamic power reduction made possible by more advanced process nodes, the increasing complexity of designs results in a real challenge to get power consumption back in control.
To address this power challenge, a solution is to select a multiple voltage architecture with blocks running independently at different voltages depending on the operating modes and frequency targets. However, this demands a complete solutions for all elements of the logic design.
The solution is introduced with the AURA generator of single port memory registers (1PRFile) by Dolphin Integration.
The AURA generator of single port memory registers (1PRFile) is optimized to generate instances with the minimum die size while satisfying speed requirement up to 400 Mhz. The AURA generator is also designed to minimize power:
Data retention mode
Dynamic Voltage and Frequency Scaling (DVFS) with continuous voltage range between 1.2 V +/-10% and 0.9 V +/-10%
- Power reduction features
- Flexible architecture
- Ultra high speed
- Decrease of fabrication costs
- Decrease of Time-To-Market
- Optimal Design for Yield