Implementing a SoC with a minimal number of metal layers can be a major challenge for SoC integrators of some highly constrained circuits: standard cell libraries are very hard to route in 1P3M and finding 1P3M memories is a challenge which most SoC Integrators face on the own...
Fortunately, the solution is introduced with the CALYPSO architecture of One Port Register File, designed to complement the absolutely highest density uHD-BTF standard cell library.
CALYPSO incorporates the latest architectural innovations from Dolphin Integration, for designing a compact and reliable 3LM memory architecture.
CALYPSO leaves metal 4 and above free to ensure more efficient place and route and to reduce significantly the overall die-cost of application such as image sensors devices integrating SoC with only 2 or 3 metal layers available for routing.
- Flexible architecture
- Reduced die cost
- Power reduction features
- Decrease of Time-To-Market
- Part of the “1P4M Top Panoply”
- Optimal Design for Yield