The S80 offers high system throughput and efficient memory utilization.
The internal registers provide 208 bits of read/write memory that is accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of exchange instructions makes either a set of main or alternate registers accessible to the programmer. The alternate set allows operation in a foreground/background mode or it may be reserved for very fast interrupt response.
The S80 also contains a stack pointer, program counter, two index registers, a refresh register (counter) and an interrupt register. All output signals are fully decoded and timed to control standard memory or peripheral circuits. With interface macros it can be connected to the existing Z80 peripheral family.
- The S80 is an 8-bit parallel processing CPU that is functionally compatible with the Zilog Z80
- Internal 16-bit, fully synchronous parallel processing CPU
- S80 has pipelined architecture that uses approximately one quarter of the clock cycles when compared to the Zilog Z80
- Using interface macros, the S80 can be connected to the existing Z80 peripheral family
- The instruction set contains 158 instructions and is fully compatible with Zilog Z80 at the object code level
- The S80 is pipelined and typically uses a quarter of the clock cycles when compared to the Z80
- Synthesizable Verilog RTL
- Verilog testbench and scenarios
- Synthesis scripts
- User documentation