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SATA Device side with ARM AMBA bus

The SATA Device core includes the Link and Transport digital logic and analog PHY with configurations fully compliant with the SATA I specifications. It is ideal for system on a chip (SOC) designs for Disk drives, storage systems, NAS and RAID systems. The Device core supports internal ARM AMBA bus interface for data transfers within disk controller SoCs. It also supports bus master DMA rates of 1.5 Gbps burst rates.

Features

Compliance

SATA 1.0 specification
SATA 2.0 specification

SATA PHY Data Rates

1.5 Gbps & 3.0 Gbps
Supports PIO & DMA modes
Supports bus master DMA

ARM AMBA AHB Inteface

Revision 2.0

Available Hardware Features

Extended SATA cable lengths
BIST for PHY operation

Deliverables

Deliverables - Digital:

Verilog RTL
Synthesis scripts
Timing scripts
Simulation environment
Test vectors (where applicable)
Clocking requirements
Software drivers (where applicable)

Deliverables - Analog:

LEF file
Spice simulation
GDSII
Behavioral Verilog model
Synopsis .lib file

Documentation:

Detailed design documents
Application Notes

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device-side SATA-to-AMBA bus core - Transport

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SATA Device side with ARM AMBA bus

Features

Deliverables

View SATA Device side with ARM AMBA bus full description to...

device-side SATA-to-AMBA bus core - Transport

Get full access to this IP datasheet

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