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SATA PHY
The SATA PHY is comprised of a hardened GDSII Physical Medium Attachment (PMA) sublayer containing the SerDes, plus a soft Physical Coding Sublayer (PCS) Verilog module that is connected to the hard macro at the PMA interface. The PCS, when coupled with the hardened PMA SerDes macro, provides a Serial ATA PHY with compliant signals for the end customer. Since the VSL PHY family includes many test features and capabilities that are not part of the Serial ATA specification, additional pins from the PMA layer are also available.
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Block Diagram of the SATA PHY IP Core
SATA PHY IP
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- 32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- 32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- SATA 6G PHY in SMIC (40nm, 28nm)
- SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
- SATA 6G PHY in UMC (40nm, 28nm, 22nm)