The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller is a highly configurable Device Controller compatible with SD Physical Layer Specification Version 3.01, SDIO Specification 3.0 and eMMC Specification Version 4.51. The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller supports SPI, SD 1, 4 bit modes and eMMC 1, 4, 8 bit modes. The Core is designed to operate at a maximum frequency of 208MHz for SD and 200MHz for eMMC. The simple and flexible interface of PE-SMID controller enables the user to integrate effectively in any SOC system or with any system bus interface. The controller supports both Boot and Alternate Boot Mode Operation.
The controller supports AHB Interface and works in DMA Mode of operation to transmit and receive data. The AHB Slave Interface provides the operational registers for Processor to configure the PE-SMID controller. This controller also adds the flexibility to connect the Flash memory with all inputs as required.
The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller Core is designed for low power, high performance,
less gate count making it ideal for low-power and high-performance applications. The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller core was tested using rigorous verification methodology, consisting of directed tests, constrained random verification, and Error Injection cases.
The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller Core has a very simple firmware interface. The core comes with an optimized software programming model, allowing any customer to meet their high system performance requirement while maintaining low CPU overhead. The architecture supports all security features such as Card Lock Password protection, Write Protection and also an optional Authentication based Content Protection. Cyclic Redundancy Code (CRC) Integrity checking is handled in Hardware. CRC7 is used for Command and CRC16 is for Data Integrity.
The SD 3.01 / SDIO 3.0 / eMMC4.51 Device Controller is suited for a variety of applications such as:
- Mobile Phones
- HD Video
- Content Protection Recorded Media (CPRM)
- Compliant with
- Part1 SD Physical Layer Specification Ver3.01
- Part E1 SDIO Specification Version 3.00
- Part A3 ASSD SDA Core Specification Ver1.00
- Part A1 ASSD Extension Specification Ver2.00
- Part3 Security Specification Ver3.00
- Part1 eSD (Embedded SD) Addendum Ver 2.10
- JESD84-B451 eMMC 4.51 Specification
- AMBA Specification 2.0
- eMMC - Supports HS200 mode
- Boot Protection
- Supports MMC Dual Data Transfer
- Supports Boot / Alternate Boot Mode.
- Supports Discard and Sanitize Commands.
- Supports eMMC4.5.1 Security Protocol Commands
- Supports SD Bus Width 1-bit, 4-bit , SPI Mode and MMC Bus Width 1/4/8
- Supports SDIO 2 Functions and easily scalable to 7 Functions Supports SDR12, SDR25, SDR50, SDR104 and DDR50 modes Supports SD Memory Access Up to 2TB (SDXC)
- Supports SDXC, SDHC, MMC plus, MMC Mobile Cards
- Supports CMD20 for Speed Class Recording
- Supports Password Protection of Cards Supports Secure Erase Mechanism
- Supports Replay Protected Memory Block Supports
- DMA operation for high speed data transfer
- Configurable 32-bit FIFO buffers (512B – 2kB)
- Dual-Buffer mode optimizes throughput
- Supports packed commands, Context ID and Data tag needed for e2MMC devices
- Data Transfer Rate SD – Up to 104Mbyte/sec eMMC – Upto 200MBytes/sec
- Clock support – SD - 208 MHz / MMC-200MHz AHB Clock – Up to 300MHz (process dependent)
- Lowest Gate Count – 27.71K
- Complete Solution – IP, HW & SW Development Kit, Onsite support
- Lowest Power / Highest Performance at System Level
- Scalable Architecture, Multiple Interface Options
- Application Level Expertise
- World Class Professional Support.
- Fully Synthesizable RTL
- Unencrypted Source Code
- Self-checking Test bench and Testcases
- Verification specification
- User Documentation
- Integration Manual
- Simulation Scripts –NC-Verilog, VCS, Modelsim ,QuestaSim
- ASIC/FPGA Synthesis scripts
- Loopback Client Driver
- SD3.0/eMMC4.51 Host Driver
- Onsite Support
Block Diagram of the SD3.01 / SDIO 3.0 / eMMC 4.51 Device Controller IP Core