SD3.01/SDIO 3.0/eMMC 4.51 Host Controller IP Core

Features

• Compliant with
• Part1 SD Physical Layer Specification Ver3.01
• Part E1 SDIO Specification Version 3.00
• Part A3 ASSD SDA Core Specification Ver1.00
• Part A1 ASSD Extension Specification Ver2.00
• Part3 Security Specification Ver3.00
• Part1 eSD (Embedded SD) Addendum Ver 2.10
• JESD84-B451 eMMC 4.51 Specification
• AMBA Specification 2.0
• Supports SD Bus Width 1-bit, 4-bit , SPI
• Mode and Optional 8bit mode for SDIO
• embedded applications
• Supports eMMC HS200 Mode
• Supports Tuning Sequence for HS200 Mode
• Data Tag Mechanism and Packet Commands
• support for eMMC.
• Supports SDR12, SDR25, SDR50, SDR104,and DDR50 modes
• Supports SD Memory Access up to 2TB (SDXC)
• Supports CMD20 for Speed Class Recording
• Supports Clock Tuning
• Supports eMMC Boot Operation and
• Alternate Boot Operation mode
• Entire Core can run on Low Power Clock during power saving mode
• SD Clock Gating
• Supports SDSC / SDHC / SDHS / SDXC Cards
• Supports Up to 7 Slots
• Supports SDIO features Multi-block,
• Suspend/Resume, Read Wait and Master
• power Control
• Supports SD features Erase, Password
• Protection and Write protection feature
• Supports Asynchronous Interrupt for data transfers
• Supports PIO / SDMA and ADMA Operation
• Cyclic Redundancy Check (CRC) for command and data
• Configurable 32-bit FIFO buffers (512B –2KB)
• Data Transfer Rate
• SD – Up to 104Mbytes/sec
• eMMC – Up to 200Mbytes/sec
• SD Clock – Up to 208 MHz
• eMMC Clock – Up to 200MHz
• AHB Clock – Up to 300MHz (process dependent)

Benefits

• Highly Configurable IP
• Highly Customizable
• Low Gate Count
• World Class Support

Deliverables

• Fully synthesizable RTL
• Self-checking Test-bench and Testcases
• Verification specification
• ASIC/FPGA synthesis scripts
• User Documentation
• Integration Manual

Block Diagram of the SD3.01/SDIO 3.0/eMMC 4.51 Host Controller IP Core