PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU, loop-backs, LOL, LOS, Equalizer, LA, line rate output driver.
The serdes (except 32 bit I/Os) is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate.
The data signal in the deserializer is applied to a 50Ω terminated data input is equalized to restore the data eye by the bandwidth limited media such as transmission lines on FR-4 PCBs or coaxial cable. The selectable equalizer can be tuned for the best performance with particular media. An automatic offset control with overriding option (manual or FEC directed) is built in for correcting of duty cycle distorted data such as in fiber optic receivers. The LA following the equalizer is conditioning the data eye for robust CDR operation. CDR phase as well as its dynamics can be adjusted to meet specific jitter tolerance and jitter transfer specifications. Line rate data (8.5-11.3Gb/s) is deserialized to 32-bit parallel data stream and converted to CMOS format for feeding into a FEC or other digital processing block or for feeding out (LVDS output buffers are necessary). LOL and LOS with programmable thresholds are built in for loss of lock and loss of signal indication.
In the serializer the 32 bit wide data stream (CMOS levels) coming from a FEC or another digital block is converted to differential CML levels, serialized and retimed to remove even/odd bit distortion, shape the eye and remove jitter. Serial data is shipped out through a differential 50Ω terminated (each output) data buffer. Multiple dividers (including fractional N) are implemented in the CMU for support of different clocking modes: 79:85, 85:79 (FEC+G.709) 14:15, 15:14 (FEC only) 237:239, 239:237 (G.709 only) 255:239, 239:255 (add FEC to G709 frame). VCXO PLL is included for convenient reference clock generation by using an external high quality oscillator.
All biasing currents are programmable within +/-30% for operational margin estimation in production. DC test points are integrated for measurement of internal temperature, bias voltages and ground potential. Loop backs to/from serializer are integrated for link testing purposes. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
- Data-rates from 8.5Gb/s to 11.3Gb/s.
- High sensitivity input (15mV SE p-p)
- Adjustable input signal equalizer
- Clock and Data Recovery
- Low power consumption (200mW)
- 1.2V and 1.6V Power Supply
- LOS and LOL detection
- Clock synthesizer (including ∑Δ)
- Input and output 50Ω termination
- Adjustable (+/-30%) reference current
- DC test points.
- Integrated temperature sensors
- Manual and automatic offset control
- Stand-by mode
- CDR bandwidth & phase adjustment.
- Line rate loop backs
- Clock monitor output
- Output swing 400mV or 250mV p-p SE
- Output data line rate retiming
- VCXO control PLL
- GDS, netlist, documentation, schematics, testbench.