The I2MS-1011 is designed to support serial interfaces with various I2C-compliant hosts and devices. The I2MS-1011 can be configured to operate either in master or slave mode. The IP core is designed to support an 8-bit data bus with single or bursts transfers based on the data size configured in the control register. All transfer protocols required for I2C operation are performed automatically by hardware, including the two-way acknowledgment of data character receipt. The IP core supports multi-master arbitration, and the arbitration success or failure is indicated through a status bit.
The I2MS-1011 is designed to connect to AMBA bus, and it can interface to most peripheral expansion buses. The IP core can be integrated into the SOCP-1110 Open-Silicon SoC Platform as a library component.
- Supports the synchronous inter-integrated circuits (I2C) master and save protocol
- Configurable to operate in master or slave mode
- Generates start, stop, repeated start and ACK.
- Detects start, stop, repeated start, and busy state
- Supports multi-master arbitration
- Programmable clock rate
- Option to skip transmission of device address in-case of single host or device
- Programmable device address width up to 8-bit
- Programmable address width up to 8-bit
- One-byte write and read buffer
- Sequential (burst) byte-read and byte-write capability
- Supports standard and fast mode
- Compliant to AMBA 2.0 specifications