The HIP 3300 Serial RapidIO IP solution is a complete high-performance core that incorporates a logical layer, a transport layer, and a physical layer according to the RapidIO specification ver 2.1. HIP3300 IP core also supports I/O and message-passing. The core provides a Serial RapidIO interface on one side and ARM's AMBA 3 AHB, high performance interface on the other side of the core, allowing felxible and high performance communication with host CPU. Modular design of the IP core
allows easy implementation of add-on third party bus interfaces and/or other standard bus interface. IP core also has internal multi-channel DMA desciprot based, controller that fully exploits AHB protocol features and thus supports highest available data throughput and back to back packet transmissions.
- Conforms to the latest RapidIO Interconnect specification – Rev.2.1
- AMBA 3 AHB ARM CPU host interface, for high performance on-chip communication.
- Supports multiple high speed lanes, (1x, 2x, 4x, 8x and 16x modes).
- Configurable modes of operation; 1.25 Gbaud/s, 2.5 Gbaud/s, 3.125 Gbaud/s, 5Gbaud/s, 6.25Gbaud/s transfer rates.
- Internal multi-channel DMA, descriptor based,controller that fully exploits AHB protocol features and thus supports highest available data throughput and back to back packets transmission.
- Configuration and Status Register File containing over 40 architectural registers providing total software control of IP core.
- Number of software maskable interrupt request signals.
- Full backward compatibility with RapidIO specification revision 1.3
- Provides roadmap to future RapidIO specification revisions.
- IP core version with AMBA AXI interface is option
- Highly Configurable
- Modularized for IP reuse
- Fully synchronous
- Clearly defined clock domains
- Layered architecture
- Single or multi-use license
- Verilog RTL source code
- Comprehensive documentation package
- Functional specification
- User guide