Serial Video Receiver, including for CMOS Image Sensors complying with MIPI CSI2 and/or SMIA CCP2 standards. Up to four data lanes can be supported.
The core is available
- CSI2 Mode functionality highlights include:
- Configurable 1 or 2 data lanes;
- Up to 1Gbps per lane;
- Interface signals as defined in Appendix B of MIPI CSI2 specifications;
- All CSI functionality implemented in hardware, freeing the CPU to other tasks
- Support of all data formats.
- Extensive set of registers, accessible by AMBA APB bus
- Programmable timing parameters
- CCP2 Mode functionality highlight include:
- Class 0, 1 and 2;
- Up to 650Mbps;
- Supporting all data formats as defined in Chapter 5 of the CCP2 Specifications
- Receiver Behavior as recommended in Chapter 8 of the CCP2 Specifications.
- Byte-Limit counter beyond SMIA specifications for better error recovery
- Verilog RTL
- Verilog test patterns
- Detialed specifications of the analog PHY
- Detailed documentaion