This SerDes PHY macro is designed in TSMC 40nm technology to meet the SFI-S standard and is CEI 11G-SR compliant. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. This hard macro can be paired with Cadence CA-SD0050 TX macro as shown in diagram above. The macro will operate from 0ºC to 125ºC and is designed for a flip-chip package.
- SFI-S standard, CEI 11G-SR compliant, and OIF-SFI5-01.02 support
- This macro is configured as 11 lanes RX channels
- Capable of max data rates from 9.95 to 11.2 Gbps per lane.
- This macro can be paired with Cadence’s CA-SD0050
- Clock recovery with greater than +/- 100 PPM tracking range
- On demand eye diagram curve measurement capability.
- On-chip phase lock loop (PLL) with selectable reference clocks
- Meets SFI-S 500ps lane-to-lane skew budget for RX and TX
- AMBA interface for programming parameters
- BIST functions for manufacturing test
- Standard Integration Views
- Integration Support