This SerDes PHY macro was designed in 40nm technology to meet the SFI-S standard and is CEI 11G-SR compliant. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. Hard macros for the TX, RX, Common blocks and various macro assemblies of up to 10 TX and RX channels are available. The macro will operate from 0șC to 125șC and is in a flip-chip package.
- SFI-S standard, CEI 11G SR compliant, and OIF-SFI5-01.02 support
- This macro is capable of transmitting and receiving max data rates from 9.953 to 11.2 Gbps per lane.
- Clock recovery with greater than +/- 100 PPM tracking range
- On demand eye diagram curve measurement capability.
- On-chip phase lock loop (PLL) with selectable reference clocks
- Separate RX and TX lanes for multi-lane macro flexibility
- Meets SFI-S 500ps lane-to-lane skew budget for RX and TX
- AMBA interface for programming parameters
- BIST functions for manufacturing test including multiple pattern generator/error detector
- Analog Test Bus for test and characterization
- Standard Integration Views
- Integration Support