The OL_MPEG4 core family includes hardware implementations of single and multi-channel implementations of the MPEG-4 algorithm.
The core accepts a full resolution video stream as input and outputs encoded bitstreams.
Simple, fully synchronous design with low gate count.
- Full resolution video (beyond 4CIF (704x576) @ 30 fps) support.
- Very low operational frequency : from ~3 MHz for QCIF @ 15 fps.
- Multi-channel version proven in silicon. Single channel version proven in FPGA.
- Motion vector up to –16.0/+15.5 pixels with single and bidirectional search (I, P & B pictures).
- Glueless interface to SDRAM for frame storage (a single 16 Mbit or 64 Mbit SDRAM chip with 16 bit data bus is sufficient for most applications).
- The processor includes IEEE-1180 compliant DCT/IDCT and quantizer/dequantizer.
- Supports YCbCr 4:2:0 raster video input
- The core outputs MPEG-4 bitstreams.
- Min Clock speed = 8 x the raw pixel clock speed
- Simple, fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- Synthesizable VHDL or Verilog RTL.
- Bit accurate C model.
- Complete HDL testbench.
- Complete data sheet.