The CEVA-TeakLite is a 16-bit fixed-point general-purpose DSP core. It is designed for low power, low voltage and high-speed Digital Processing applications. The core is an ideal solution for-low power, speech and audio processing, wireless communication (GSM, CDMA, TDMA, EDGE, GPRS, 3G, etc.), modems, advance telecommunication systems, disk drive controllers and various embedded control applications.
The CEVA-TeakLite and CEVA-Oak are architecturally identical and therefore the CEVA-TeakLite is fully binary code compatible with the CEVA-Oak DSP core. Ina addition, the CEVA-TeakLite is assembly backward compatible to the CEVA-Pine.
Since the CEVA-TeakLite and CEVA-Oak are architecturally identical from the programmer view, it effectively eliminates the need to recompile or rewrite existing software modules during migration from the Ceav-Oak to the CEVA-TeakLite.
The CEVA-TeakLite is fully synthesizble ('Soft Core') and is process independent designed. It is easily portable to any ASIC library. The core is designed to be used as an engine for DSP-based Application Specific ICs (ASIC), and is available as a DSP core in a standard cell library, To be utilized as a part of the user's custom chip design. As such, it provides several levels of modularity in RAM, ROM and I/O, allowing efficient DSP based ASIC development. The core is designed in a single edge clocking system which allows the use of full or partial scan testing methodologies. The core supports Emulation, Debugging and Testing via JTAG.
- Soft Core (process and library independent).
- Available also as a Hard Macro Low Voltage operation, down to one volt.
- Low power consumption Three modes of operation:
- Active mode
- Slow mode - linearly reduces clock speeds and current consumption by a factor N (user defined factor)
- Stop mode - leakage current only Fully Static Design. Cool CEVA-TeakLite version - optimized for very low power consumption.