The Single-Port AHB NAND-Flash controller IP Core supports both SLC & MLC Nand-Flash memory devices in 8-bit or 16-bit configuration.
The AHB interface supports all kind of transfers. As the Nand-Flash memory device is slower than the AHB data bus, all data transfers are processed through an external buffer (embedded 32-bit RAM Block). Typically the size of the RAM is equal to the size of one nand-flash page (1, 2, 4 or 8 x 528-bytes). However, the controller is able to work efficiently with pages larger than RAM size.
The Single-Port AHB NAND-Flash controller IP Core is able to boot on code located in nand-flash memory by automatically fetching the code (boot configuration defined by static input pins).
The AHB NAND-Flash controller can perform error detection & correction. Both Reed-Solomon and Hamming algorithms are available.
According to the application requirements, the generic parameters listed in Table 3 can be configured before synthesis, allowing customers to make the best possible trade-off between performance and area.
- Single-Port AMBA AHB 2.0 bus-compatible;
- Supports SLC & MLC Nand Flash memory devices;
- Generates Boot Sequence;
- Supports handshake signals to interface with an external DMA Controller;
- Error Correction: Reed-Solomon or Hamming;
- All parameters programmable through APB Interface;
- Very low power consumption can be obtained by gating clock for ECC;
- Able to interface with an EBI (External Bus Interface);
- All data transfers are processed through an external buffer memory;
- Best trade-off performance/area by defining generic parameters before synthesis;
- Compiled simulation model;
- Verilog RTL sources;