This PLL is designed for audio clock generation. The reference clock is either 12MHz crystal or the input clock. It supports 256*fs and 128*fs clock output, where fs is the audio system’s sample rate of 8k/11k/12k/16k/22k/24k/32kHz/44.1kHz/48kHz/192k. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.