The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists of 32-bit blocks using 128-bit key and IV.
Basic core is very small (7,500 gates). Enhanced versions are available that support UEA2 and UIA2 confidentiality an integrity algorithms.
The design is fully synchronous and available in both source and netlist form. Test bench includes the ETSI/SAGE SNOW 3G test vectors.
SNOW3G1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
- Keystream generation using the SNOW 3G Algorithm
- High throughput: up to 7.5 Gbps in 65 nm process
- Small size: from 7.5K ASIC gates
- Satisfies ETSI SAGE SNOW 3G specification
- Outputs keystream in 32-bit data blocks
- Uses 128-bit key and IV
- Completely self-contained: does not require external memory
- Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
- Deliverables include test benches
- By far the smallest SNOW3G1 core on the market
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- User Documentation