SPC (Synthesizable Programmable Core) is a soft FPGA core, fully integrated into standard design flows, that allows the seamless use of programmable logic in ASICs and SOCs.
The IP comprises three main scalable sub-modules :
- A programmable core based on look up table (LUT) interconnected through configurable networks.
- A configuration interface allowing the interaction with the IP and the loading of the bitstream.
- A Built In Self Test block for standalone manufacturing testing.
- Address / data Control word interface.
- ATPG compatibility mode.
- BIST engine.
- Test vectors for manufacturing.
- Logic Compilation
- From RTL source (Verilog, VHDL, SystemVerilog) to bitstream.
- Timing driven place and route.
- TCL shell support for flexible use.
- Fully integrated into user's RTL SOC design flow
- Highly scalable and customizable
- Technology independent
- Performance driven architecture
- No programmable logic knowledge required
- Independent configuration storage device (Flash, Non Volatile Memory, Fuse ...)
- Verilog programmable IP comprising : Synthesizable RTL including Bitstream loader and BIST module
- Synthesis, simulation and STA scripts
- ADICSYS compilation software : Acompile
- Test patterns
- Constraint files
- Documentation and Examples
- Possibility to deliver a hard block (GDSII).
Block Diagram of the Soft eFPGA IP