The Xelic SONET/SDH Concatenated STS-192c/STM-64 Framer Core (XCS192C) aligns incoming SONET/SDH frames and provides transport overhead processing, path overhead processing and pointer processing for contiguous concatenated SONET/SDH payloads types. The XCS192C contains independent Transport Processor and Concatenated Path Processor modules with dedicated external ports for overhead insertion and extraction. Incoming/outgoing data is transferred at an STS-192c/STM-64 rate using a 64-bit data bus operating at 155.52Mb/s.
- Suitable for FPGA and/or ASIC implementations.
- Supports Transport Processing, Path Overhead Processing and Concatenated Pointer Processing functions.
- Provides for bypass and normal modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Inserts transport and path overhead through internal register programming and/or external overhead ports.
- Provides transmit facility and terminal loopback options for diagnostic purposes.
- Provides automatic REI insertion for B2 parity errors detected in the XCS3C Receive Processor.
- Allows for the insertion and extraction of programmable 1, 16 or 64 byte section and path trace messages.
- Supports programmable fixed payload data insertion and checking for diagnostic purposes.
- Provides flexible frame alignment capability with programmable options for OOF and LOF algorithm state transitions. Diagnostic capability is provided to force LOF and OOF state conditions.
- Provides a variety of saturating performance counters (configurable for bit or block type) for the accumulation of various error conditions.
- Interprets and extracts F1, APS, S1 (optional byte or nibble detection) overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
- Detects LOS, LOF, LOA, OOF, TIM, TIU, B1 error, SD, SF, B2 error, AIS-L, and RDI-L conditions and provides optional interrupt generation.
- Provides concatenated pointer interpreter functionality with programmable state machine operation including the 8 of 10 pointer objective and single AIS state transition options for flexible configurations.
- Detects and accumulates pointer interpreter increments, decrements, and NDF events.
- Interprets incoming path RDI overhead information (provides programmable accept and unstable counts) and provides detection of RDI-P, ERDI-P, and path RDI unstable errors with maskable interrupt capability
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).