IQ-LinkSPI is a frame-based wrapper for the SPI interface. It is designed to receive frames containing commands for the bus operations and the wrapper configuration.
- Configurable SPI mode of operation and chip select polarity
- Mode 0 (CPOL=0, CPHA=0)
- Mode 1 (CPOL=0, CPHA=1)
- Mode 2 (CPOL=1, CPHA=0)
- Mode 3 (CPOL=1, CPHA=1)
- Detection of errors using a 16-bit CRC (CCITT)
- Decoupled command and response interfaces, allowing for high efficiency of the communication.
- FIFO-based interface with configurable depth, allowing a trade-off between resource use and maximum number of commands issued before receiving responses.
- Easy adaptation to the various FPGAs and various design requirements (ranging from slow, low-budget interfaces to the high bandwidth applications)
- Integrated DMA memory master supporting low-overhead burst transfers
- Master bus interfaces: AMBA AHB, Avalon
- Allows easy access to internal bus over a standard SPI interface.
- Encrypted RTL source code
- User manual
- Implementation guide