Amidst a rich ŕ-la-carte offering, shCODlp-100.02 is an optimized and complete configuration around high performance DAC and ADC cores which provide a higher SNR for the smallest silicon area.
Fabless companies targeting high fabrication volume would benefits from shCODlp-100.02 optimization for 0.11 µm optically shrunk processes.
- Feature completeness:
- ADC SNR of 95 dB and 100 dB for the DAC
- 2 line-in and 1 microphone-in with AGC
- 1 headphone driver and 1 line-output to drive external power amplifier
- A mixer with “record while listening” function
- Simplest Bill of Material
- Maximized yield with the best trade-off between silicon area and SoC / PCB costs
- The headphone output application schematics is capacitor-less
- The line-out application schematics is filter-less
- PLL-less: single master clock generates all sampling frequencies.