The Xelic SONET/SDH Multi-Rate Framer/LAPS Mapper Core (XCS12CLM) aligns incoming SONET/SDH frames and provides transport overhead processing, path overhead processing, pointer processing, and LAPS mapping in compliance with the ITU-T X.86/Y.1323 specification.
The XCS12CLM contains independent SONET/SDH Transport Processor, Concatenated Path Processor, and LAPS Processor modules with a configuration option for STS-3/STM-1 or STS-12/STM4 SONET/SDH frame rates. Incoming/outgoing SONET/SDH data is transferred using a clock valid scheme with a line side clock rate up to 100Mb/s using an 8-bit data bus.
The XCS12CLM Transmit Transport Processor inserts transport overhead blanking, calculates and inserts framing, B1/B2 parity (with corruption capability), and scrambles SONET/SDH frames. An external DCC overhead port is provided to insert section and line DCC information into generated SONET/SDH frames. Diagnostics support includes optional corruption of inserted parity, LOS insertion, and scrambling enable/disable capability. MS AIS insertion is also provided. APS information is optionally insertion through input signaling. The Transmit Concatenated Path Processor inserts high order path overhead blanking, configurable Path Signal Label (C2 Byte) information, calculates and inserts B3 parity (with corruption capability), and supports pointer increments and decrements. Pointer SS bit field insertion is provided through input signaling. AISP can be forced through external signal control. The LAPS Transmit Processor interprets incoming ethernet packets and performs rate adaptation through the insertion of rate adaptation sequence characters and LAPS frame flags. Incoming client ethernet packets are processed with valid and invalid packet detection provided. Invalid packets are optionally indicated in the LAPS frame through the insertion of an escape sequence or the inversion of the FCS field. Ethernet packets are encapsulated into generated LAPS frames. Address, control, SAPI and FCS field information is inserted into outgoing LAPS frames. Transparency is provided by replacing specific LAPS field information data with appropriate control sequence bytes. A configurable interframe gap is provided through the insertion of flags to achieve a specified spacing between LAPS frames. Diagnostics support includes optional continuous LAPS flag generation, test frame insertion, corruption of inserted FCS field information and scrambling enable/disable capability.
The XCS12CLM Receive Transport Processor contains a frame alignment unit with OOF and LOF algorithm state transitions. Incoming frames are descrambled (optional) and aligned for transport overhead processing. Transport overhead interpreters are implemented to detect error conditions which include LOS, LOF, OOF, B1 errors, B2 errors, and MS AIS. Diagnostics support includes optional corruption of calculated parity, and descrambling enable/disable capability. An external DCC overhead port is provided to extract section and line DCC information from generated SONET/SDH frames. APS information is extracted each frame and provided through output signaling. The Receive Concatenated Path Processor detects Path AIS, LOP, Pointer Increments, Pointer Decrements, Pointer NDF’s, and Pointer 3 in a row conditions in addition to B3 error detection. The LAPS Receive Processor performs LAPS frame descrambling, delineation, and removes all flags including interframe gaps. Rate adaptation information is removed and transparency processing translates control sequence information and removes appropriate control bytes. FCS address, control, SAPI, and FCS fields are examined for errors and reported through external signaling. LAPS frame interpreters provide test frame detection, FCS error detection, frame abort sequence detection, and invalid control sequence detection. Support is provided for configurable LAPS frame address, control, and SAPI field mismatch detection. A client FIFO interface is provided with Start of Packet (SOP), End of Packet (EOP), data valid, valid packet, and invalid packet signaling.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCS12CLM core available under flexible single use licensing terms with netlist or source code deliverables.
- Compliant with ITU X.86/Y.1323 Specification.
- Provides full duplex operation with independent transmit and receive functionality.
- Supports configurable STS-3/STM-1 and STS- 12/STM-4 SONET/SDH frame rates.
- Supports transport and path overhead blanking.
- Supports optional SONET/SDH frame scrambling/Descrambling capability for diagnostic purposes.
- Calculates and inserts B1/B2/B3 parity information with optional corruption capability.
- Provides capability to force MS AIS or LOS insertion.
- Contains external overhead port for section/line DCC insertion/extraction.
- APS information is optionally insertion through input signaling.
- Provides capability to force pointer increment and decrement operations.
- Supports pointer SS bit insertion.
- Provides capability to force path AIS.
- Supports configurable interframe gap capability.
- Provides configurable test frame insertion and continuous LAPS flag insertion options for test purposes.
- Calculates and inserts LAPS FCS with corruption capability for test purposes.
- Supports transparency and optional extended transparency processing.
- Performs rate adaptation through the insertion of Rate Adaptation Sequence (0x7ddd) and Flags.
- Provides LAPS frame invalid packet indication through configurable abort sequence insertion or FCS inversion.
- Provides LAPS frame Start of Frame (SOF), and End of Frame (EOF), interframe gap, rate adaptation, and transparency signaling indicators.
- Optional LAPS self synchronous scrambler/ descrambler operation.
- Provides frame alignment capability with OOF and LOF algorithm state transition signaling.
- Supports optional SONET/SDH frame descrambling.
- Detects LOS, LOF, OOF, B1/B2/B3 error, and MS AIS conditions.
- Calculates and compares extracted B1/B2/B3 parity for all incoming SONET/SDH frames.
- APS information is extracted for each frame and provided through output signaling.
- Detects LOP, pointer interpreter increments, decrements, pointer NDF, and pointer 3 in a row events.
- Performs delineation on incoming LAPS frames.
- Provides status signals for LAPS test frame detection, incoming flag detection, rate adaptation sequence detection, transparency sequence detection, FCS error detection, frame abort sequence detection, and invalid control sequence detection.
- Supports configurable LAPS frame address, control, and SAPI field mismatch detection.
- Provides client FIFO interface with Start of Packet (SOP), End of Packet (EOP), data valid, valid packet, and invalid packet detection signaling.