STS48/STM16 Pointer/Path Processing to STS1 level

Features

• Suitable for FPGA and/or ASIC implementations.
• Integration support and maintenance available.
• XCS48PP core available under flexible single use licensing terms with netlist or source code deliverables.
• Supports bypass, loopback, and normal modes of operation.
• Implements 16-bit register interface for programming of internal registers.
• Compliant with ITU-T G.707 and Telcordia GR-253- CORE Specifications.
• Supports processing for any mix of payloads ranging from a granularity of STS-1 to STS-48c including nonstandard concatenation types.
• Provides transmit/receive facility and terminal loopback options for diagnostic purposes.
• Provides transmit and receive pointer interpreter/generation functionality with programmable state machine operation including the 8 of 10 pointer objective and single AIS state transition options for flexible configurations.
• Detects and accumulates pointer interpreter or pointer generator increments, decrements, and NDF events.
• Inserts/extracts channelized high order path overhead through internal register programming and/or an external overhead port.
• Supports auto generated or synchronized frame start (telecom bus or frame start signaling) generation.
• Allows for blanking of all high order path overhead (except H4) locations.
• Provides automatic path REI insertion (bit or block mode options) for B3 parity errors detected in the XCS48PP Receive Processor.
• Allows for the insertion of programmable 1, 16 or 64 byte trace messages.
• Calculates and inserts B3 parity information with optional corruption capability.
• Supports transmit/receive Tandem Connection source or sink configurations with programmable Incoming Signal Fail (ISF) detection and maskable interrupt reporting.
• Allows for programmable automatic insertion of single bit or enhanced path RDI for the detection (Receive Processor) of Path Alarm Indication Signal (AIS-P), Loss of Pointer (LOP-P), Path Trace Identifier Mismatch (TIM-P), Path Trace Identifier Unstable (TIU-P), Path Unequipped (UNEQ-P), and Path Signal Label Mismatch (PLM-P) conditions.
• Interprets transmit and receive incoming multiframe information and supports optional AIS-P insertion for programmable LOM detection with maskable interrupt reporting.
• Supports programmable fixed payload data insertion down to STS-1 granularity for diagnostic purposes.
• Provides programmable diagnostics capability to force AIS-P, VC-AIS, RDI-P, and pointer generator increment, decrement, or NDF conditions.
• Detects AIS-P, LOP-P, FIFO overflow and underflows, SS bit mismatch, TC-REI, and telecom bus parity errors with maskable interrupt reporting.
• Includes 16-bit saturating performance counters (configurable for bit or block type) for the accumulation of B3 errors with programmable threshold capability (including optional error sync update option). Provides optional interrupt generation for B3 error, signal degrade (SD) and signal fail (SF) detection.
• Includes 16-bit saturating performance counters (configurable for bit or block type) for the accumulation of REI-P errors with programmable latch and clear or incoming error sync capture options. Optional maskable interrupt generation is provided for REI-P error detection.
• Provides programmable automatic insertion of Path Alarm Indication Signal (AIS-P) for the detection of Path Trace Identifier Unstable (TIU-P), Path Trace Identifier Mismatch (TIM-P), Signal Degrade (SD), Signal Fail (SF), Path Signal Label Unstable, Path Unequipped (UNEQ-P), and Loss of Multiframe (LOM).
• Provides path trace interpreter with programmable trace accept and unstable counts for message lengths of 1, 16 or 64 bytes. Optional maskable interrupt generation is provided for Path Trace Identifier Mismatch (TIM-P) and Path Trace Identifier Unstable (TIM-P) error detection.
• Interprets and extracts F2, F3, and K3 (optional byte or nibble detection) path overhead information to internal register locations with programmable accept and unstable maskable interrupt capability.
• Interprets incoming path RDI overhead information (provides programmable accept and unstable counts) and provides detection of RDI-P, ERDI-P, and path RDI unstable errors with maskable interrupt capability.