The USB3.0 Device controller IP Core implements the standard Link Layer, Protocol Layer and Application Layer. It provides a GMAC interface on the application end. It uses PIPE interface to connect to USB3.0 PHY. USB2.0 core is also included and integrated to allow backward compatibility.
The USB3.0 Device controller comes with driverless Gmac application ported on a Xilinx spartan6 FPGA board. The validation platform can also be used for developing customer specific applications.
The USB3.0 to Gigabit Ethernet reference design can also be licensed. This ready to go solution offers customers a ready solution to enter the USB3.0 to Ethernet based solutions.
- USB3.0 compliant device, backward compatible to USB2.0 Device
- PIPE Interface to connect to PHY
- GMAC interface on application end
- Single memory block for OUT transfers
- Option of using single vs. multiple memory blocks for IN transfers as a tradeoff between performance vs. area
- Supports Control, Bulk, Isochronous and Interrupt endpoints
- Endpoint streaming supported
- 32-bit data paths
- Software configurable descriptors
- Number of interfaces and endpoints and their types can be configured at RTL integration
- 250MHz clock at PHY interface and 125 MHz for rest of the operation
- The IP core comes with an Evaluation platform that fully demonstrates the USB3.0 to Gigabit ethernet application. Clients can run IPERF, ping tests and upload download regression tests. This enables the customer to be fully satisfied of the performance of the IP core in a real life application. The evaluation boards also enable easy integration of customer's custom application using the dual onboard connectors for external daughter cards.
- The IP is ready to be taped out for any application and comes with Aizyc's integration support included in the price of the IP License.
- Synthesizable Verilog RTL
- Test bench and exhaustive Test cases
- Synthesis constraints and script files
- Sample APB Slave Driver
- Documentation – User Manual, Verification plan , Validation Report, Synthesis, DFT and Integration Guidelines
- Evaluation platform based on Xilinx Spartan 6 FPGA
- Sample USB3.0 to Gigabit Ethernet application (no drivers needed)