True Circuits, Inc. IP Catalog
True Circuits, Inc.
True Circuits offers a complete family of standardized and silicon-proven clock generator, deskew, low bandwidth and spread spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs are available in a range of frequencies, multiplication factors (1-4096), sizes and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs from other vendors. Our DLLs are available in mutli-slave and multi-phase versions and delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature, are ideal for high-speed DDR interface applications and are available in different sizes and form factors. Customized solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GlobalFoundries, UMC and Common Platform processes from 180nm to 28nm. Customers can license our timing IP either directly from TCI or through our global network of design services partners and sales reps. The hard macros are available for a per use license fee with reuse options and no royalty fees. The license fee includes integration support from TCI or our partners to ensure a successful customer tape out. The deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, Library Exchange Format (LEF) files and extensive user documentation.
True Circuits, Inc. IP Listing
854 Products Listed in the following categories
Clock Generator PLL
Low Banwidth PLL
Spread Spectrum PLL
General Purpose PLL