Denali's Databahn Synthesizable DDR-SDRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR-SDRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Denali's PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
- Supports DDR3/2/1 and LP-DDR1/2 devices
- Synthesizable GHz DDR PHY — 1066 MHz in 4 hours!
- Contains all DDR timing logic, single DLL
- Complete DFI to I/O pad connections
- Full place and route flow with basic layout and routing
- Configurable and synthesizable
- Configurable design to match application interface
- Flexible I/O pad placement
- Fully synthesizable with automated CTS
- Complete SDC and STA flow for optimized timing closure with standard place and route flows
- Extensive Silicon-proven track record
- PHY slice-based architecture with all views, not a "black box"
- DFI (DDR PHY Interface) compliance
- Support for 8 or more ranks of memory, including DIMM support for large enterprise systems
- Support for varied foundry processes
- Optional integrated analog DLL has fine delay step granularity (15ps or less)
- Highly configurable (data width, ECC, I/O selection, I/O, and pad-ring placement)
- Support for flip chip or wirebond pads IEEE 1149.1 boundary scan
- Integrated I/O pads from multiple vendors
- At-speed built-in loopback test
- Denali's GHz PHY is synthesizable and RTL-based, making a perfect fit for your physical chip characteristics and simplifying back-end implementation, carries an extensive silicon-proven track record, and is DFI-compliant, supporting the industry's interface standard.
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