The Xelic Optical Transport Network (OTN) Time Sliced Flex Framer Core (XCO3F) performs Framer/Deframer functions and OTUk/ODUk/OPUk overhead processing for any combination of ODU0, ODU1, ODU1e, ODU2, ODU2e, ODUFlex, and ODU3 frame rates that combined provide a throughput up to 40Gb/s. The XCO3F supports dynamic time slice reconfiguration without interruption to existing provisioned traffic. The XCO3F contains independent Transmit and Receive processors with time sliced external ports for overhead insertion and extraction with support for ODUk streaming and payload mapping modes of operation for all the above specified frame rates. Delay Measurement capability is provided in both Transmit (PM/TCMi) and Receive (TCMi) processors. Client and Line side data transfers use read enable and data valid signaling at clock rates up to 180 MHz to allow for flexible system clocking schemes. A flexible data bus architecture is used for ODUk/OTUk transport to provide 256-bit transfers for FPGA applications and 128-bit transfers for ASIC implementations.
The XCO3F Transmit Processor inserts OTUk, ODUk, and OPUk overhead, calculates and inserts parity, automatically generates Backward Defect Indication (BDI) signaling, and scrambles generated frames for all provisioned time slices. Support is provided for both asynchronous mapping procedure (AMP) and generic mapping procedure (GMP) justification methods. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM), Path Monitoring (PM), and Tandem Connection Monitoring (TCM) overhead insertion. The XCO3F supports up to 6 levels of tandem connection overhead insertion and Interpret for all time slices. Diagnostics support includes optional corruption of inserted parity and maintenance signal insertion. Programmable payload support includes asynchronous, bit synchronous, GFP, null test, and PRBS mapping types.
The XCO3F Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOFLOM algorithm state transitions for all provisioned time slices. Incoming OTUk or ODUk frames are descrambled (optional) and aligned for OTN time sliced overhead processing. OTUk, ODUk, and OPUk overhead information is extracted to both time sliced internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, OOM, and LOFLOM. Support is provided for both asynchronous mapping procedure (AMP) and generic mapping procedure (GMP) justification methods. OTU AIS, ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. FTFL and up to 6 levels of TCM insertion and interpret is provided. OPUk payload type mismatch error conditions are detected and support is provided for programmable payload type accept and inconsistent thresholds.
Performance counters (configurable for error sync mode) are provided for the accumulation of inserted (XCO3F transmit processor) and detected (XCO3F receive processor) positive and negative justification events along with BIP-8 parity and BEI errors for OTU SM, ODU TCMi, and ODU PM (XCO3F receive processor) for all provisioned time slices. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO3F provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO3F core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Provides for streaming and normal modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Supports transmit and receive facility and terminal loopback configurations.
- Support is provided for both asynchronous mapping procedure (AMP) and generic mapping procedure (GMP) justification methods.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains, source RTL, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).