Triple Timer Counter

Features

• Three independently programmable 16-bit timer/counters
• Internal (pclk) or external clock source (one for each timer/counter)
• 16 bit prescaler, for clock speed selection
• Interrupt generated either on overflow or at regular intervals
• Three output waveforms, one from each counter (generated using overflow or interval and Match_1 interrupts)
• An Event Timer measures length of each external clock pulse (high or low duration)
• Counters can be incrementing or decrementing
• Current value of each count register can be read at any time
• Targeted at a pclk speed of 100MHz (0.25um technology), with external clock speed maximum of pclk/2

Deliverables

• Synthesizable Verilog RTL
• Verilog testbench and scenarios
• Synthesis scripts
• User documentation