The Low Bandwidth PLL is designed to multiply an input clock by a fixed-point number between 1 and 16 with a low adjustable loop bandwidth. It does not provide any deskew functionality. The low loop bandwidth provides filtering of reference input jitter. It contains a 1-16 divider at the reference clock input, a 1-16 integer divider and a 1-256 fractional divider in the internal feedback path, and a 1-8 divider at the output. The loop bandwidth is inversely controllable with a relative range of 1-256. The outputs are 50% duty cycle for all output divider values.
- Designed to address the problem of excessive system clock jitter originating from lower-quality crystals.
- An adjustable bandwidth allows the designer to dial-in the desired amount of period jitter filtering. The bandwidth is adjustable as a precise fraction of the reference frequency.
- Feedback divider with 8 fractional bits allows the frequency to be set more precisely when the bandwidth is reduced.
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines