TSMC CLN28HP 28nm Low Banwidth PLL - 350MHz-1750MHz

The Low Bandwidth PLL is designed to multiply an input clock by a fixed-point number between 1 and 16 with a low adjustable loop bandwidth. It does not provide any deskew functionality. The low loop bandwidth provides filtering of reference input jitter. It contains a 1-16 divider at the reference clock input, a 1-16 integer divider and a 1-256 fractional divider in the internal feedback path, and a 1-8 divider at the output. The loop bandwidth is inversely controllable with a relative range of 1-256. The outputs are 50% duty cycle for all output divider values.