UDP/IP Hardware Protocol Stack Core

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming even in processor-less SoC designs. The core can be configured to operate as a full-duplex Transmitter/Receiver, or as Transmitter-only or Receiver-only to minimize silicon footprint.

Trouble-free network operation is ensured through run-time programmability of all the required network-parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity.

The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming -capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. The core is Ethernet MAC-independent, but is available pre-integrated with CAST, Altera, Xilinx, or other third-party eMAC core.